1. Field of the Invention
The present invention relates to liquid crystal display devices, and more particularly, to an array substrate for reflective and transflective liquid crystal display devices.
2. Description of the Background Art
Generally, a reflective liquid crystal display device does not need to equip an additional light source such as a back light because it can substitute an external light source for the back light. A transflective liquid crystal display device has both properties of the reflective liquid crystal display device and a transmissive liquid crystal display device. Because the transflective liquid crystal display device utilizes both of the back light and the external light source, it can save power consumption.
FIG. 1 illustrates a liquid crystal panel for a conventional transflective liquid crystal display device. The conventional transflective liquid crystal display device 11 has an upper substrate 15 that includes a color filter 18 a transparent common electrode 13 and a lower substrate 21 that includes a pixel region “P”, a pixel electrode 19, thin film transistor and an array of gate lines 25 and data lines 27. The color filter 18 includes a black matrix 16 and sub-color filters R, G and B. The pixel electrode 19 has a transmission portion “A” and a reflection portion “PR”. Liquid crystal 23 is interposed between the upper substrate 15 and the lower substrate 21. The lower substrate 21 is also referred to as an array substrate with thin film transistors “T”, switching elements, arranged in a matrix on the array substrate 21. A plurality of horizontal gate lines 25 and a plurality of vertical data lines 27 cross each other defining the pixel region “P”. If the transparent pixel electrode 19 and the transmission portion “A” are omitted from the transflective liquid crystal display device, it becomes a reflective liquid crystal display device.
FIG. 2 is a plan view illustrating a partial array substrate for a conventional reflective liquid crystal display device. As shown in the figure, a plurality of gate lines 25 and a plurality of data lines 27 cross each other defining a pixel region “P”. A thin film transistor “T” is formed at a crossing portion of the gate line 25 and the data line 27. The thin film transistor “T” usually includes a gate electrode 32, a source electrode 33, a drain electrode 35 and an active layer 34. A pixel electrode 19 is formed in the pixel region “P” and the thin film transistor “T” connected to the drain electrode 35 drives the liquid crystal 23 of FIG. 1. A reflective electrode, which is formed of opaque conductive metal having a high reflexibility, is substituted for the pixel electrode 19 in the reflective liquid crystal display device. The opaque conductive metal is selected from a group consisting of aluminum (Al) and aluminum alloys (AlNd, for example), for example.
Because the reflective liquid crystal display device uses an external light source, incident light from the external light source passes through the upper substrate (not shown) and is then reflected at the reflective electrode 10 on the array substrate 21. The reflected light subsequently passes through the liquid crystal and thereby polarization properties of the light are changed according to birefringence properties of the liquid crystal. Color images can be displayed when the light passing through the liquid crystal colors the color filter.
FIG. 3 is a cross-sectional view taken along III-III of FIG. 2 according to the conventional art. As shown in the figure, a gate electrode 32 and a gate line 25 of FIG. 2 are formed on a substrate 21. A gate insulating layer 41 is formed on the substrate 21 and on the gate electrode 32. An active layer 34 is formed on the gate insulating layer 41 and partially overlapped with a source electrode 33 and a drain electrode 35. The source electrode 33, the drain electrode 35 and the data line 27 are formed on the active layer 34. A thin film transistor includes the gate electrode 32, the source electrode 33, the drain electrode 35 and the active layer 34. A passivation layer 43 made of insulating material is formed on the thin film transistor. The passivation layer 43 is subsequently patterned to form a drain contact hole 45 exposing a part of the drain electrode 35. A reflective electrode 19 contacts the drain electrode 35 through the drain contact hole 45. The material for the reflective electrode 19 is selected from a group including aluminum (Al) and aluminum alloy (AlNd, for example), etc.
FIG. 5 is a cross-sectional view taken along line V-V of FIG. 4 according to the conventional art. A thin film transistor “T” including a gate electrode 32, a source electrode 33, a drain electrode 35 and an active layer 34 is formed and a first passivation layer 43 is formed on the thin film transistor “T”. The first passivation layer 43 is formed by depositing a transparent organic insulating material such as benzocyclobutene (BCB) and acrylic resin. A drain contact hole 45 that exposes a part of the drain electrode 35 is formed and a etching hole 53 is formed by etching the first passivation layer 43 corresponding to the transmission hole 53 in the pixel region “P”. A reflective electrode 19a that contacts the drain electrode 35 through the drain contact hole 45 is formed in the pixel region “P”. The reflective electrode 19a is formed of aluminum (Al) and aluminum alloys (AlNd, for example), etc. A second passivation layer 47 is formed on the reflective electrode 19a and patterned to expose the reflective electrode 19a corresponding to the drain contact hole 45. The second passivation layer 47 is formed of insulating material such as silicon oxide (SiO2) or silicon nitride (SiNX), for example. A transparent pixel electrode 19b that contacts the exposed reflective electrode 19a through the patterned second passivation layer 47 is formed on the second passivation layer 47.
Several masks for patterning array elements of the array substrate are used in the manufacturing of the conventional reflective and transflective liquid crystal display device. An align key for accurate aligning of the mask and the substrate is formed on the corner of the substrate simultaneously with the gate line or the data line forming process. The shape of the align key has unevenness. Accordingly, a detector aligns the mask and the substrate by irradiating light onto the uneven surface of the align key and sensing the light reflected from the surface of the align key.
FIG. 6 is a plan view illustrating a partial array substrate having a coplanar type polysilicon thin film transistor for a conventional transflective liquid crystal display device. A gate line 71 and a data line 84 cross each other defining a pixel region “P” and a thin film transistor “T” is formed at a crossing portion of the gate line 71 and the data line 84. The thin film transistor “T” is a polysilicon thin film transistor that includes a polysilicon active layer and has a coplanar structure in which a gate electrode 70 is formed under a source electrode 80 and a drain electrode 82. A gate pad 74 and a data pad 86, which receive an external signal, are formed respectively at one end of the gate line 71 and the data line 84. The gate pad 74 and the data pad 86 respectively contact a gate pad terminal 94 and a data pad terminal 96 that are formed of transparent conductive material. The thin film transistor “T” includes the gate electrode 70, the source electrode 80, the drain electrode 82 and an active layer 66. The active layer 66 has an active layer expanded portion 67 in the pixel region “P”. A storage line 72 is formed parallel to the gate line 71 with a same material as that of the gate line 71 and has a storage line expanded potion 73 in the pixel region “P”. The pixel electrode 63 contacts the drain electrode 82. A storage capacitor portion “C” and a reflection portion “PR” are formed in the pixel region “P”. A reflector 102 is formed on the storage capacitor portion “C”. The rest potion of the pixel region “P” except the reflector 102 is a transmission portion “F”.
FIGS. 7A to 7F are cross-sectional views taken along IV-IV, V-V, VI-VI of FIG. 6 illustrating a fabricating sequence of an array substrate according to the related art. In FIG. 7A, a first insulating layer 62 is formed on a substrate 60 by depositing inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNX) and an amorphous silicon layer 64 is formed on the first insulating layer by depositing amorphous silicon (a-Si:H). The first insulating layer 62, referred to as a buffer layer, is for preventing an expansion of alkaline substances from the substrate 60. The amorphous silicon layer 64 is crystallized into polysilicon by introducing a solid phase crystallization (SPC) method, a metal induced crystallization (MIC) method, a laser annealing method and a field effect metal induced crystallization (FEMIC) method.
In FIG. 7B, a semi-conductor layer 66 is formed by patterning the crystallized layer and a gate insulating layer 68, a second insulating layer, is formed on the semi-conductor layer 66. A conductive metal layer is subsequently formed on the gate insulating layer 68. A gate electrode 70 and a gate line 71 of FIG. 6 are formed by patterning the deposited conductive metal layer. The semi-conductor layer 66 has a semi-conductor layer expanded portion 67 in the pixel region “P”. The gate pad 74 is formed at one end of the gate line 71. The storage line 72 is simultaneously formed parallel to the gate line 71 and the storage line 72 has the storage line expanded portion 73 on the pixel region “P”.
The semi-conductor layer 66 can be divided into two regions, one is a first active region “A” and the other is a second active region “B”. The first active region “A” is a pure silicon region and the second active region “B” is an impure silicon region. The second active regions “B” are positioned at both sides of the first active region “A”. The gate insulating layer 68 and the gate electrode 70 are formed on the first active region “A”. After forming of the gate electrode 70, ion doping is performed onto the second active region “B” to form a resistant contact layer. The gate electrode 70 serves as an ion stopper that prevents dopants from penetrating into the first active region “A”. After the ion doping is finished, the semi-conductor layer 66, the polysilicon island, implements a specific electric characteristic, which varies with types of the dopants. If the dopant is, for example, B2H6 that includes a Group III element, a doped portion of the polysilicon island 66 becomes a p-type semiconductor. Whereas, if the dopant is PH3 that includes a Group VI element, the doped portion of the polysilicon island 66 becomes an n-type semiconductor. A proper dopant should be selected to satisfy the use of a device. After the dopant is applied onto the polysilicon island 66, the dopant is activated.
In FIG. 7C, a third insulating layer 76, i.e, an interlayer insulator, is formed over the whole area of the substrate 60 and is patterned to form a source contact hole 78a and a drain contact hole 78b. A source electrode 80 and a drain electrode 82, which contact the second active region “B” through the source contact hole 78a and the drain contact hole 78b, respectively, are formed by depositing and then patterning conductive metals such as aluminum (Al), aluminum alloys, tungsten (W), copper (Cu), chromium (Cr) and molybdenum (Mo), etc. A data line 84 that contacts the source electrode 80 is simultaneously formed and a data pad 86 is formed at one end of the data line 84. The polysilicon thin film transistor “T” is formed through the above processes.
In FIG. 7D, a fourth insulating layer 88 is formed on the whole area of the substrate 60 and then the thin film transistor undergoes a hydrogenation process. The hydrogenation process is for removing defects that occurred on the surface of the active layer 66. A fifth insulating layer 90 is formed on the fourth insulating layer 88 using transparent organic insulating material such as benzocyclobutene (BCB) or acrylic resin. A first drain contact hole 92 exposing the drain electrode 82, a gate pad contact hole 91 exposing the gate pad 74 and a data pad contact hole 95 exposing the data pad 86 are formed by patterning simultaneously the laminated layers.
In FIG. 7E, a pixel electrode 93 that contacts the exposed drain electrode 82 and is extended to the pixel region, a gate pad terminal 94 that contacts the exposed gate pad and a data pad terminal 96 that contacts the exposed data pad are formed on the fifth insulating layer 90 using transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), for example.
In FIG. 7F, a sixth insulating layer 98 is formed on the whole area of the substrate 60 using silicon oxide (SiO2) or silicon nitride (SiNX), for example. A second drain contact hole 100 that exposes the pixel electrode 93 contacting the drain electrode 82 is formed by patterning the sixth insulating layer 98. A reflective electrode 102, which contacts the exposed pixel electrode 93, is formed on the sixth insulating layer 98 using conductive metal such as aluminum (Al) or aluminum alloys, for example. A first etching hole 104 that exposes the gate pad terminal 94 and a second etching hole 106 that exposes the data pad terminal 96 are formed by patterning the sixth insulating layer 98. The reason for exposing the gate pad terminal 94 and the data pad terminal 96 in the last process is to prevent the pixel electrode 93 and the reflective electrode 102 from being etched together in etching solution during an etching process for the reflective electrode 102.
Conventional reflective or transflective liquid crystal display devices have some problems described as follows. First, because a reflective electrode is formed on an organic insulating layer such as benzocyclobutene (BCB) and the contact property of the reflective electrode and the benzocyclobutene (BCB) layer is not good, the reflective electrode may not be stably deposited on the organic insulating layer. This lacks of stability lowers electric properties of a liquid crystal panel. Second, when a sputtering process is used for forming the reflective electrode on the benzocyclobutene (BCB), accelerated electrons collide into the surface of the benzocyclobutene (BCB) and separate the benzocyclobutene (BCB) particles from the surface, which produces benzocyclobutene (BCB) particles in a deposition chamber. The benzocyclobutene (BCB) particles in the deposition chamber contaminate the deposition chamber. Lastly, an align key may not be detected by a detecting apparatus if the benzocyclobutene (BCB) is deposited on the substrate and covers the align key. Accordingly, alignment error of a mask and the substrate may be occurred during a light exposing process for patterning the reflective electrode.